Parasitic Ringing Suppression in FPGA-Controlled Three-Phase Voltage Source Inverter Using RC Snubber Circuit

Angga Wahyu Aditya; Fathur Zaini Rachman; Andi Sri Irtawaty; Desak Made Ristia Kartika; Indra Ferdiansyah; Muhammad Rizani Rusli

doi:10.33019/jurnalecotipe.v13i2.4597

Authors

Angga Wahyu Aditya Department of Electrical Engineering, Balikpapan State Polytechnic
Fathur Zaini Rachman Department of Electrical Engineering, Balikpapan State Polytechnic
Andi Sri Irtawaty Department of Electrical Engineering, Balikpapan State Polytechnic
Desak Made Ristia Kartika Department of Civil Engineering, Balikpapan State Polytechnic
Indra Ferdiansyah Department of Electrical Engineering, Politeknik Elektronika Negeri Surabaya
Muhammad Rizani Rusli Department of Electrical Engineering, Politeknik Elektronika Negeri Surabaya

DOI:

https://doi.org/10.33019/jurnalecotipe.v13i2.4597

Keywords:

FPGA, Induction Motor, Parasitic Element, RC Snubber Design, VSI

Abstract

Parasitic phenomena in inverter circuits, arising from semiconductor switching devices, are a well-recognized challenge that causes voltage spikes, high-frequency oscillations, and PWM signal distortions, thereby reducing the reliability of electric motor drive systems. Unlike prior studies that address snubber design without explicitly deriving parasitic parameters, this work presents a systematic approach to RC snubber design based on analytically derived parasitic inductance and resonance frequency parameters. A series-parallel RC snubber is designed for each semiconductor switch using mathematical models for spike voltage, resonant frequency, snubber capacitance, and damping resistance. Experimental validation is conducted using a three-phase inverter with a switching frequency of 25 kHz, controlled by a Field Programmable Gate Array, and connected to an electric motor. Without the snubber, ringing reaches approximately 70–75% of the nominal PWM voltage, and current spikes exceed 33% of the peak value. After applying the designed snubber, oscillations are reduced to approximately 1.5–1.8% of the nominal PWM voltage, and current spikes are confined below 10% with an oscillation duration of less than 1 millisecond. These results demonstrate that the analytically designed snubber effectively suppresses parasitic ringing, reduces switching stress, and improves inverter stability and motor control accuracy under high-frequency PWM operation.

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